The present invention relates to a dynamic random access memory.
The memory cells of a dynamic random access memory (hereinafter referred to as DRAM) are each composed of one transfer transistor and one cell capacitor. In one memory cell, one-bit data, that is, "0" data or "1" data is stored. The data in the memory cell is determined depending on whether or not charges are accumulated in the cell capacitor.
However, the charges accumulated in the cell capacitor gradually leak out from the cell capacitor with the lapse of time. Thus, in a memory cell in the cell capacitor of which charges have been accumulated by writing, the amount of charges in the cell capacitor gradually reduce after the writing. If this state is left as it is, then the data stored in the memory cell changes.
Thus, in the case of a DRAM, in the state in which the power supply is ON, the data in the memory cells thereof is read out before the data is changed due to the leakage of the charges therein, and accurate data is written into the memory cells, that is, the data refresh operation is performed.
The refresh operation is carried out in the following procedure.
On the basis of the address generated by a refresh counter in the chip, the rows of the memory cell array are selected one by one in due order. In the row thus selected, a high potential is applied to the word line, so that the transfer transistors in the memory cells connected to the word line are turned on. Thus, from each of the memory cells belonging to the selected row, the data (the absence or presence of charges in the cell capacitor) is read out onto the bit line. The data thus read out onto the respective bit line is amplified by a sense amplifier and written into the memory cell again.
The refresh operation must be performed before the data in the memory cells is changed due to the leakage of the charges therein. Thus, here the following terms are defined in connection with the refresh operation:
Refresh cycle (C): The cycle number of refresh operations which must be performed in order to refresh all the memory cells. In case, by one refresh operation, one row is selected, the cycle number thereof is equal to the number of rows in the memory cell array.
Refresh interval (t ri): The interval between the refresh operations performed for one and the same memory cell which interval is determined on condition that the data in the memory cell be not changed by the leakage of the charges in the cell capacitor. This interval is equal to the time spent for the values of the refresh counter to make one round.
Refresh period (t rp): The period of time spent for one refresh operation.
The refresh cycle C, the refresh interval t ri, and the refresh period t rp have the following relationship among them: EQU t ri=t r.times.C (1)
For instance, in the case of a 64-Mbit DRAM having a memory capacity of 64 megabits, the number of rows is 4,096, so that the refresh cycle C becomes 4,096. The refresh interval t ri is 64 ms. In this case, the refresh period t rp becomes about 15,625 .mu.s.
In recent years, mobile computers such as notebook personal computers etc. are rapidly becoming popular. The feature of a mobile computer lies in the point that it can be freely used anywhere, and therefore, in the use thereof, a battery is used as the power source of the mobile computer in many cases.
Therefore, the increase in the length of time during which the battery can be continuously used becomes an important matter to the mobile computer.
In order to increase the time length of continuous use of the battery, it is sufficient to increase the capacity of the battery or to reduce the power consumption of the circuits (such as, e.g. CPU, memories, etc.) in the computer.
For instance, the technical measure of stopping the operation of the memories in the computer when no signal is inputted for a certain fixed time from input devices such as the keyboard, the mouse, etc. contributes to the reduction in power consumption of the mobile computer.
However, the DRAM used as the main memory of the computer must be periodically refreshed, as mentioned above, in order to prevent the loss of the data.
Thus, what is called the average current I ave for refresh will be defined below, through which examination will be made of the power consumption caused by the refresh operation.
The average current I ave is defined by the following equation (2): EQU I ave={I row.times.t ac.times.C}/t ri (2)
wherein I row: Current which flows when one row is accessed to perform a refresh operation. PA1 wherein yi stands for the width (in the column direction) of one row decoder, PA1 Ni stands for the number of spare row decoders in one block (8 sub-arrays), and PA1 X stands for the length (in the row direction) of the chip. PA1 448.times.(7+1)=3,584 fuses PA1 (75+7.21)/75=1.096
t ac: Time for which one row is accessed. PA2 C: Refresh cycle. PA2 t ri: Refresh interval.
The average current I ave for refresh means the average value of the current used when refresh is performed. Therefore, in order to reduce the power consumed when a refresh operation is performed, it is sufficient to reduce the average current I ave for refresh.
For instance, the average current for refresh in a 64-Mbit DRAM will be examined below. In the case of a commercially available 64-Mbit DRAM, I row is 100 mA, t ac is 80 ns, C is 4,096 cycles, and t ri is 64 ms.
Therefore, the average current I ave for refresh is obtained, in accordance with the above-given equation (2), as follows: EQU I ave={100 mA.times.80 ns.times.4,096}/64 ms EQU =about 512 .mu.A.
According to the specifications of DRAMs with low power consumption in 1996, the average current I ave for refresh is required to be 250 .mu.A or below. The average refresh current of the above-mentioned 64-Mbit DRAM is about 512 .mu.A, which does not conform to the specifications.
In order to satisfy the above-mentioned specifications, it is sufficient, according to the above-indicated equation (2), to reduce I row and t ac or to increase t ri. However, I row and t ac are factors relating to the basic performance of the DRAM, and therefore, it is difficult to alter them. Thus, in order to reduce the average refresh current I ave, it is the best choice to increase the refresh interval t ri.
More concretely, in order to make the average refresh current I ave less than 250 .mu.A, the refresh interval t ri must be made at least 2.sup.2 times as large as 64 ms, that is, 256 ms.
However, if the refresh interval t ri is increased, then the interval between the refresh operations performed for one and the same memory cell is increased. Due to this, in the case of a memory cell which has a poor retention (pause) characteristic, that is, a memory cell in which the speed at which the charges leak from the cell capacitor thereof is high, the data is inverted before the refresh thereof is performed in some cases.
In order to prevent the occurrence of such a trouble, in the case of a conventional DRAM, a memory cell having a poor retention characteristic, that is, a memory cell having a retention time (the time for which charges in an amount not below the threshold value can be retained) of 256 ms or below is recognized as a defective memory cell as in the case of a memory cell which is structurally defective.
Therefore, a row or a column including a memory cell which has a retention defect is replaced with a spare row or a spare column by a redundancy circuit so that all the memory cells may have a retention time of 256 ms or more.
In this way, in the conventional DRAM, the refresh interval t ri is increased, and thus, the average refresh current I ave is reduced, whereby the power consumption during the execution of a refresh operation is reduced. Further, the problem that memory cells having retention defects are increased as a result of increasing the refresh interval t ri is overcome by substituting spare cells for those memory cells which have retention defects.
However, the number of defective memory cells (defective rows or defective columns) which can be relieved by means of a redundancy circuit has its limit. This point will be further described below.
For instance, it is to be assumed that there are 200 (on the average) memory cells which each ones have a retention time longer than 128 ms and shorter than 256 ms, and the other memory cells each have a retention time of 256 ms or longer.
Those memory cells which have poor retention characteristics, that is, the memory cells which each have a retention time longer than 128 ms and shorter than 256 ms are produced at random in the wafer. Due to this, the distribution of the memory cells which have retention defects can be expressed in the form of Poisson distribution. In this case, if 218 optional memory cells in the memory cell array (64 megabits) are replaced by spare cells, then a manufacturing yield of 90% can be obtained (computer simulation).
However, the memory cell arrays of the recent DRAMSs are each comprised of a plurality of sub-arrays. In this case, the redundancy elements, that is, the spare decoder (row or column) and the spare line (row or column) is provided for each of the sub-arrays, and the redundancy elements associated with one sub-array cannot relieve the defective memory cells of other sub-arrays.
In case the number of redundancy elements is fixed, the relief efficiency obtained when an equal number of redundancy elements are assigned to each of a plurality of sub-arrays is lower than the relief efficiency achieved when the redundancy elements are provided for one memory cell array.
For instance, with reference to 64-Mbit DRAMs, examination will be made below of a 64-Mbit DRAM comprising only a 64-Mbit bit memory cell array and of a 64-Mbit DRAM comprising thirty-two 2-Mbit sub-arrays.
Here, it is to be further assumed that, to the memory capacity of 64 megabits, 64 redundancy elements are provided.
In the case of the DRAM comprising only a 64-Mbit memory array, 64 arbitrary defective memory cells in the memory cell array can be relieved even in the worst case. On the other hand, in the case of the DRAM comprising thirty-two 2-Mbit sub-arrays, two redundancy elements are provided for each sub-array. Therefore, in the worst case, only two arbitrary defective memory cells in one sub-array can be relieved.
Thus, in the case of the DRAM comprising only a 64-Mbit memory cell array, even if 64 defective memory cells are produced concentratively in a part of the interior of the memory cell array, these defective memory cells can be relieved, whereas, in the case of the DRAM comprising thirty-two 2-Mbit sub-arrays, if three or more defective memory cells are produced within one sub-array, all the defective memory cells cannot be relieved in some cases.
According to a computer simulation using the Poisson distribution, in the case of the DRAM comprising only a 64-Mbit memory cell array (the replacement region is of 64 megabits), if it is assumed that 200 (on the average) memory cells having retention defects exist in one chip, then a manufacturing yield of 90% can be obtained by providing 218 redundancy elements.
On the other hand, in the case of the DRAM comprising thirty-two 2-megabit sub-arrays (the replacement region is of 2 mega bits), if it is assumed that 200 (on the average) memory cells having retention defects exist in one chip, then it is possible to obtain a manufacturing yield of 90% unless 14 redundancy elements are provided for each sub-array, that is, the total number of 448 redundancy elements are provided for the thirty-two sub-arrays.
Here, a concrete example of the case where one redundancy element is provided corresponding to one spare row decoder will be described.
FIG. 1 shows an example of the floor plan of a 64-Mbit DRAM. FIG. 2 shows a row decoder area.
According to this example, the memory cell array is comprised of four blocks BLK0 to BLK3 disposed in the row direction, The blocks BLK0 to BLK3 each have a memory capacity of 16 mega bits. The blocks BLK0 to BLK3 are each comprised of eight 2-Mbit sub-arrays disposed in the column direction. Thus, the memory cell array as a whole is comprised of thirty-two 2-Mbit sub-arrays.
The sub-arrays each have 512 rows (word lines) and 4,096 columns. Between the respective adjacent eight sub-arrays in each block, sense amplifier areas are disposed.
Row decoder areas are disposed at a one-side end, in the row direction, of the four blocks BLK0 to BLK3. The word lines extend from the row decoder area towards the other end in the row direction. The word lines are provided commonly in the four blocks BLK0 to BLK3. A row fuse area is disposed adjacent to the row decoders. In the row fuse area, there are formed fuses in which defective row addresses are stored.
Column decoder areas are disposed at one-side ends, in the column direction, of the respective blocks BLK0 to BLK3. Column select lines extend from the column decoder areas towards the other ends in the column direction. A column fuse area is disposed adjacent to the column decoders. In the column fuse area, there are formed fuses in which defective column addresses are stored.
As described above, in case it is assumed that, in the 64-Mbit memory cell array, 200 (on the average) memory cells having retention defects exist, 14 redundancy elements (spare row decoders) must be provided for each 2 Mbit sub-array in order to obtain a manufacturing yield of 90%.
Accordingly, in the 2-Mbit sub-array, 128 row decoders and 14 redundancy row decoders are provided.
Further, to this example, to one row decoder, four rows (word lines) are connected. Therefore, in the 2 Mbit sub-array, 512 rows (word lines) and 14.times.4 (=56) spare rows are provided.
Ordinarily, in case defective rows (word lines) are replaced by spare rows, the replacement is carried out from row decoder to row decoder. In the case of this example, to one row decoder, four rows (word lines) are connected, so that four rows are replaced by four spare rows at one time.
In the 64-Mbit DRAM having a floor plan as shown in FIG. 1 and FIG. 2, the increased amount .DELTA.S in size of the chip is evaluated in accordance with the following equation (3): EQU .DELTA.S=yi.times.Ni.times.X (3)
According to the technique in 1996, yi is about 4.4 .mu.m, X is about 11 mm, and Ni is 112 (14.times.8), so that, from the equation (3), the incresed amount .DELTA.S in size of the chip becomes as follows: EQU .DELTA.S=4.4 .mu.m.times.112.times.11,000 .mu.m=5.42 mm.sup.2.
It is considered that, in case the retention interval t ri is set to 256 ms, as seen above, in order to reduce the power consumed when a refresh operation is executed, about 200 (on the average) retention-defective memory cells which each have a retention time less than 256 ms are produced. Further, in the DRAM having thirty-two 2 Mbit sub-arrays, in order to relieve 200 memory cells having retention defects, the total number of 448 redundancy elements (spare row decoders) must be provided. Due to this, in the case of the DRAM of a floor plan as shown in FIG. 1 and FIG. 2, the chip size is increased by about 5.42 mm.sup.2.
FIG. 3 shows the redundancy elements disposed side by side with the respective sub-array.
As mentioned above, in the case of the conventional technique, memory cells having retention defects are relieved by redundancy elements. The redundancy elements each include a defective address memory, an address comparator, a spare row decoder and spare rows (spare cells, spare word lines).
The defective memories each store a defective row address therein and is comprised of, e.g. a laser-burnout fuse. In the case of this example, 128 row decoders are provided for one sub-array. Due to this, in order to specify one of the 128 (2.sup.7) row decoders, a row address signal of 7 bits must be used.
Due to this, the defective address memories each need to have at least 7 fuses (one bit is stored by one fuse) so as to be able to store the 7-bit row address signal. In actuality, the defective address memories are each composed of 7 fuses for storing the defective row addresses therein and one enable fuse indicative of whether or not these 7 fuses are programmed.
In this way, in case one defective address memory is comprised of 8 fuses, the provision of
becomes necessary for the 64-Mbit DRAM as a whole, since 448 redundancy elements exist therein.
According to the technique in 1996, the total area occupied by one laser-burnout fuse and the circuits accessory thereto is about 0.0005 mm.sup.2. Therefore, the area occupied by the 3,584 fuses in the DRAM chip becomes: EQU .DELTA.S'=0.0005.times.3,584=1.792 mm.sup.2.
If the increased area portion .DELTA.S for the spare row decoders and the increased are portion .DELTA.S' for the fuses are put together, then the total area increase of the DRAM chip becomes EQU .DELTA.S+.DELTA.S'=5.42+1.792=7.21 mm.sup.2.
According to the technique in 1996, the chip size of a 64 Mbit DRAM which has no redundance circuit is about 75 mm.sup.2.
Therefore, in the case where, in a 64-Mbit DRAM which has a memory array comprising a plurality of sub-arrays, retention defects of 200 bits on the average have occurred with reference to the memory capacity of 64 Mbits, if attempt is made to relieve the retention defects by the use of a redundancy circuit so as to achieve a manufacturing yield of 90%, then the chip size becomes larger by about 9.6% than
which is the chip size of a DRAM having no redundancy circuit.
However, this value is based on the presupposition that the defective memory cells are relieved by the use of only spare rows. In the case of relieving defective cells by the use of spare columns, the same thing is naturally applicable, too.
In the above, description has been made on the reduction in power consumption of a DRAM chip and the increase in retention-defective memory cells resulting therefrom and on the relief of retention-defective memory cells by means of redundancy elements and the resulting increase in size of the chip.
Next, other problematic points of the conventional DRAMs will be described below.
Referring to the redundancy circuit shown in FIG. 3, in case a memory cell having a retention defect has been detected through a memory cell test, the row address of the defective memory cell is programmed in a defective address memory (fuse array) by laser burnout.
An external row address signal is applied through a row address input circuit and, as a result, rendered into an internal row address, signal, which is fed to a row address multiplexer. A refresh row address signal used at the time of a refresh operation is produced by a refresh counter. The row address multiplexer outputs the internal row address signal or the refresh row address signal.
In each redundancy element, the address comparator makes a comparison between the address signal programmed in the defective address memory and the address signal outputted from the row address multiplexer.
In case the two signals have turned out to coincide with each other, a coincidence signal A becomes "H" in level, which makes the spare row decoder active. The spare row decoder applies a high potential to the spare word lines. A non-coincidence signal B becomes "L" in level, which makes the row decoder inactive. In case the two signal compared have turned out not to be coincident with each other, the coincidence signal A becomes "L" in level, which makes the spare row decoder inactive. The spare row decoder, then, applies no high potential to the spare word lines.
In case, in all the redundancy elements, the two address signals compared have turned out not to be coincident with each other, the non-coincidence signal B becomes "H" in level, which makes the row decoders active. That is, the non-coincidence signal B is set, by a precharge circuit, to "H" at the beginning, but in case the two address signals in at least one redundancy element have burned out to be coincident with each other, the non-coincidence signal B is changed from "H" to "L" in level by discharge.
In the redundancy circuit shown in FIG. 3, one address comparator is disposed in each redundancy element. Therefore, on the chip, a very long row address line C must be formed to feed the row address signal to the address comparator in each redundancy element.
Due to this, the load capacity of the row address line C is increased by the number of address comparators, and thus, a long time must be spent for transmitting the address signal to all the row decoders. Further, a very large power is consumed for charging and discharging of the row address line C, so that the power consumption of the DRAM chip as a whole is increased.
The matters mentioned above will be summed up as follows:
(1) If, in order to achieve a low power consumption at the time of a refresh operation, the refresh interval t ri is increased, then some of the memory cells which have so far been normal come to have retention defects.
(2) In case memory cells which have retention defects are relieved by the use of redundancy elements, redundancy elements which are larger in number than the redundancy elements in an ordinary DRAM must be provided in the chip. Due to this, the size of the chip is increased by an amount corresponding to the increased redundancy elements.
(3) In case the memory cell array is comprised of a plurality of sub-arrays, redundancy elements are provided for each sub-array. In this case, the relief efficiency in relieving defective memory cells (including the memory cells having retention defects) is lower than the relief efficiency of a DRAM which does not have such sub-arrays.
(4) The row address line is connected not only to the row decoder but also to the address comparators equal in a number to the redundancy elements at the row side. As a result, the load capacity of the row address line is increased, thus resulting in a delay of the row address signals. This same thing applies also to the column address line.
(5) The power consumed by the row (or column) address line is increased for the same reason as described in the foregoing Item (4).